SemiEngineering

10 stories

SemiEngineeringSiliconRandomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech) Researchers at Ruhr University Bochum , the Max Planck Institute for Security and Privacy , and Georgia Tech published “Randomized Caches in Hardware: Challenges and Trade-offs.” Abstract Excerpt…

11.03

SemiEngineeringSiliconFast, Sub-Volt HZO Ferroelectric Capacitors For DRAM-Like Memory (SNU) Seoul National University -led researchers published “Resolving the Kay–Dunn limit and the speed–endurance dilemma in ferroelectric Hf 0.5 Zr 0.5 O 2 for DRAM-class sub-volt capacitors.” Abstract…

11.03

SemiEngineeringSiliconChip Industry Technical Paper Roundup: Nov. 3 New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Meter-scale quantum interconnects between large quantum processors IBM Research…

11.03

SemiEngineeringSiliconAI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE) Researchers at Materials Center Leoben, PVA TePla , and Advanced Semiconductor Engineering ( ASE) published “AI-Based Image Enhancement Improves Detection of Interconnect Defects in Microelectronic…

11.02

SemiEngineeringSilicon3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB) Researchers at imec and Vrije Universiteit Brussels published “Embodied Emissions of 2.5D and 3D Scaling in Chipletized GPUs for Low-Carbon AI.” Abstract “GPU compute resources are scaling to support…

11.02

SemiEngineeringSiliconQuantum Interconnects Link Two 120-Qubit Processors (IBM Research) Researchers at IBM Research published “Meter-scale quantum interconnects between large quantum processors.” Abstract Excerpt : “Modular quantum architecture requires long-distance quantum…

11.02

SemiEngineeringSiliconHardware Defense Blocks Memory-Dependent Prefetcher Leakage (KU Leuven) Researchers at KU Leuven and EURECOM published “SecDMP: Provably Secure Data Memory-Dependent Prefetching.” Abstract Excerpt : “In this work, we address this gap by designing a defense that is both…

11.02

SemiEngineeringSiliconCo-Optimizing Access Points Improves Analog Placement (UT Austin) Researchers at the University of Texas at Austin published “APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement.” Abstract “Analog layout automation remains…

11.02

SemiEngineeringSiliconShift Left Is Becoming A System-Level Problem Key Takeaways: Shift left is pushing beyond verification to system-level validation. Fragmented workflows with disconnected tools and models are allowing bugs to escape even though individual…

11.02

SemiEngineeringSiliconPutting AI To The Test There are an increasing number of new EDA companies these days, and this is great news. The industry needs some new vitality, new thought leaders, people willing to take risks.

11.02

The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo